CS-534: Packet Switch Architecture

Lecture Notes, Transparencies, Exercises:

• 0.1 Technology Outlook: Switches and Interconnects [PDF]
• 0.2 Central Issues in Packet Switching: an Overview [PDF]
• 0.3 (next year) Multiplexing, Time Switching, Space Switching
• 0.4 (next year) Buffering, Statistical Multiplexing, Output Contention

• 1.1 Parallel and Serial Links, Transmission Rate and Throughput [PDF]
• 1.2 Inter-Clock Domain Communication: Elastic Buffers
• 1.3 Multiplexing, Demultiplexing, Statistical Multiplexing, Output Contention
• 1.4 Multiplexor Implementation: Point-to-Point versus Buses
• Exercises 1 (due 2 Mar.- wk.2.2): Transmission Rate, Throughput [PDF]
• Exercises 2: Turn-Around Overhead, plus topics from Chapter 2 (see below)

• 2.1 On-Chip SRAM and Power Consumption
• 2.2 Off-Chip Memory Technologies
• 2.3Time-Division Multiplexing (TDM), Time Switching, Cut-Through
• 2.4 High-Throughput Memories for Time-Switching Shared Buffers
• Exercises 2 (due 10 Mar.- wk.3.3): Cut-Through, Memory Access Rate [PDF]
• Exercises 3 (due 21 Mar.-wk.5.1): Variable-Size-Packet Segmentation Overhead [PDF soon]

• 3.1 Queueing Architectures and Head-of-Line (HOL) Blocking
• 3.2 Multi-Queue Data Structures
• 3.3 Queueing for Multicast Traffic
• 3.4 The Output-Queueing Family of Switch Architectures
• Exercises 4 (due 30 Mar.-wk.6.2): Linked-List Queue Management [PDF]
• Exercises 5 (due 6 Apr.-wk.7.2): Advanced Queue Management [PDF]

• 4.1 Space (Crossbar) and Time-Space-Time Circuit Switching
• 4.2 The Input Queueing Family
• 4.3 On-Line Crossbar Scheduling with VOQ Input Queueing
• 4.4 Variable-Size Packets, Crossbars with Reconfiguration Overhead
• 4.5 Combined Input-Output Queueing (CIOQ) - Internal Speedup
• 4.6 The Big Picture: Switch Queueing Architectures
• Exercises 6 (due 17 Apr.-wk.8.3): TST Circuit Switch Scheduling [PDF]
• Exercises 7 (due 25 Apr.-wk.9.3): Input Queueing and Crossbar Scheduling [PDF]
• Exercises 8 (due 9 May-wk.10.1): Queueing Architecture SRAM Cost [PDF]

• 5.1 Byte-Sliced Crossbar Switches
• 5.2 Benes, Clos, and Fat Trees - Inverse Multiplexing
• 5.3 Bufferless versus Buffered Switching Fabrics
• Exercises 9 (due 16 May-wk.11.1): Internal Blocking in Switching Fabrics [PDF]
• Exercises 10 (due 25 May-wk.12.2): Switching Fabric Topologies [PDF]

• 6.1 Flow Control Fundamentals
• 6.2 Credit-Based Flow Control
• 6.3 Per-Flow versus Indiscriminate Flow Control
• 6.4 Backpressure in Buffered Switching Fabrics
• Exercises 11 (due 8 Jun-wk.F): Flow control, per-flow queueing [PDF]

• 7.1 Conservation Law, Hierarchical Schedulers
• 7.2 Strict (Static) Priority Scheduling
• 7.3 Round Robin Scheduling
• 7.4 Weighted Round Robin (WFQ) Scheduling
• Exercises 12 (due on Final's Day): Output Scheduling for QoS [PDF]

Last Year:

Previous Years:

Important Notes from Sp'2003 to be Incorporated above:

Chapter 2: Basic Switching Notions

• 2.1 Output Contention, Internal Blocking, HOL Blocking
• 2.2 Statistical Multiplexing, Inverse Multiplexing
• 2.3 Switch Architecture Generations, Cut-Through

• 4.1 The Output Queueing / Shared Buffer Family

[Please refer to the bibliography pointed below:]
• 8.1 Routing Table Lookup and Flow Classification Hardware
• 8.2 Cluster, Storage, System, and smaller Area Networks
• 8.3 Network Processors
• 8.4 Optical Switching