2.1 On-Chip SRAM, Power (U.Crete, CS-534)

CS-534: Packet Switch Architecture
Spring 2005

Department of Computer Science
© copyright: University of Crete, Greece

2.1 On-Chip SRAM and Power Consumption

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On-Chip RAM floorplan

SRAM block area versus capacity --0.18 um CMOS example

On-chip SRAM power consumption per MHz --0.18 um CMOS example

Note: power consumption of two-port memories appears to be quite lower than their corresponding one-port SRAM. Normally, one would expect the per-port consumption to be similar in 1-port or 2-port memories of the same capacity and port-width. One difference between the ports in each configuration is that the single port in 1-port memories is bidirectional, while each port in these 2-port memories is unidirectional (one port is dedicated write-port, the other is dedicated read-port); it is hard for this difference by itself, though, to account for just a large discrepancy in power consumption. The reasons for this large difference are still under investigation.

On-chip SRAM access rate --0.18 um CMOS example

On-Chip packet buffer examples: cost-performance

Throughput to power consumption ratio for RAM blocks & chip-I/O

Another data point says that a typical transceiver for the two differential pairs comprising a bidirectional 3.125 GBaud (2.5 Gbit/s) link consumes approx. 300 mW when the signals are intended to cross about a meter of distance or so (over copper); attenuation and signal pre-emphasis depend on the distance that you want the signals shipped at, hence so does transceiver power consumption.

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