Chapter 2:
Link and Memory Architectures and Technology
2.1
Links, Throughput/Buffering, Multi-Access Overheads
[Slides in PDF]
[Slides Handout in PDF]
[to be done: move "cut-through" from 3.1 to 2.1.
Older text for section 2.1.1:
[Text in HTML]
[Text in PDF] ]
Exercises 2:
Transmission Rate and Throughput, Turn-Around Overhead
– same exercises as in Spring 2013:
[HTML]
[PDF]
[note - to be fixed:
exercise 2.4 is duplicated as also exercise 4.2]
Exercises 3:
Switch Generations, Cut-Through
– same as exercise 4 in Spring 2013:
[HTML]
[PDF]
[note - to be fixed: exercise 4.2 is the same as exercise 2.4]
3.3, 3.4
Multiple Queues within a Buffer Memory, Queueing for Multicast Traffic
[Slides in PDF]
[Slides Handout in PDF]
[animated PPT
for queue operations with free-block preallocation]
6.3
Buffer Space versus Number of Flows
[Slides - PDF]
[Slides Handout - PDF]: [Updated 16 May 2015.]
[Alternative source, containing a subset of above material,
mostly in a similar form --in a few cases formatted slightly better:
ACACES 2007
(Third International Summer School on
Advanced Computer Architecture and Compilation for Embedded Systems)
- Slides for the course on
"Queue and Flow Control Architectures for Interconnection Switches",
by Manolis Katevenis, Part 4 of 4, in PDF:
[Slides]
[Handouts]
Flow and Congestion Control in Switching Fabrics]
Chapter 7:
Output Scheduling for Quality-of-Service (QoS) Guarantees