CS-534: Packet Switch Architecture

Exercises:

• Exercise set 1 (due week 2 --24 Feb. 2003): Rate and throughput calculations.
• Exercise set 2 (due week 3 --5 Mar. 2003): TST circuit switch scheduling.
• Exercise set 3 (due week 4 --12 Mar. 2003): Internal blocking, cut-through, switch generations.
• Exercise set 4 (due week 6 --24 Mar. 2003): RAM access rate, packet segment rate.
• Exercise set 5 (due week 7 --31 Mar. 2003): Segmented packets in linked-list multi-Q mem.
• Exercise set 6 (due week 8 --9 Apr. 2003): Linked-list queue management.
• Exercise set 7 (due week 9 --16 Apr. 2003): Queueing Architecture SRAM Cost.
• Exercise set 8 (due week 10 --7 May 2003): Input Queueing and Crossbar Scheduling.
• Exercise set 9 (due week 11 --approx. 14 May 2003): Switching Fabric Topologies.
• Exercise set 10 (due week 13 --26 May 2003): Flow control, per-flow queueing.
• Exercise set 11 (due week F --04 Jun. 2003): Output Scheduling for QoS.
• Reading Assignments: papers to be read and orally presented in class by individual students.

Lecture Notes and Transparencies:

• 0.1 Issues Overview
• 0.2 Introduction to the Course
• 0.3 Point-to-Point versus Shared Medium Links

• 1.1 Serial versus Parallel Transmission
• 1.2 Digital Telephony, TDM, Circuit Switching

• 2.1 Output Contention, Internal Blocking, HOL Blocking
• 2.2 Statistical Multiplexing, Inverse Multiplexing
• 2.3 Switch Architecture Generations, Cut-Through

• 3.1 On-Chip SRAM
• 3.2 Off-Chip Memory Technologies
• 3.3 Clock Domains and Elastic Buffers
• 3.4 Multi-Queue Data Structures
• 3.5 Queueing for Multicast Traffic

• 4.1 The Output Queueing / Shared Buffer Family
• 4.2 Shared Buffer and High-Throughput Memory Implementation
• 4.3 The Input Queueing Family
• 4.4 On-Line Crossbar Scheduling with VOQ Input Queueing
• 4.5 Combined Input-Output Queueing (CIOQ) - Internal Speedup

• 5.1 Byte-Sliced Crossbar Switches
• 5.2 Benes, Clos, and Fat Trees - Inverse Multiplexing
• 5.3 Bufferless versus Buffered Switching Fabrics

• 6.1 Flow Control Fundamentals
• 6.2 Credit-Based Flow Control
• 6.3 Per-Flow versus Indiscriminate Flow Control
• 6.4 Backpressure in Buffered Switching Fabrics

• 7.1 Conservation Law, Hierarchical Schedulers
• 7.2 Strict (Static) Priority Scheduling
• 7.3 Round Robin Scheduling
• 7.4 Weighted Round Robin (WFQ) Scheduling

[Please refer to the bibliography pointed below:]
• 8.1 Routing Table Lookup and Flow Classification Hardware
• 8.2 Cluster, Storage, System, and smaller Area Networks
• 8.3 Network Processors
• 8.4 Optical Switching