CS-534: Packet Switch Architecture
Spring 2003		 Department of Computer Science
© University of Crete, Greece

4.2   Shared Buffer and High-Throughput Memory Implementation

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There is a Crossbar inside every Switch

High-Throughput Buffer: Interleaved Memory

Multiplexing the Switch Ports onto a single Memory Port

Wide-Memory Implementation:

Time-Multiplexing the Switch Ports on a Wide Memory Port

Wide Memory

Pipelined-Memory Implementation:

Pipelined Memory

  • Animated illustration of the Pipelined Memory operation: click here.

    Control of the Pipelined Memory

    VLSI Implementation the Pipelined Memory

    Reference:
    M. Katevenis, P. Vatsolaki, A. Efthymiou: "Pipelined Memory Shared Buffer for VLSI Switches", Proceedings of the ACM SIGCOMM '95 Conference, Cambridge, MA USA, 30 August - 1 Sep. 1995, pp. 39-48; http://archvlsi.ics.forth.gr/sw_arch/pipeMem.html . FORTH, Crete, Greece (1994): USA patent number 5,774,653 of 30 June 1998.

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    Last updated: 9 May 2003, by M. Katevenis.