CS-534: Packet Switch Architecture
Spring 2003		 Department of Computer Science
© University of Crete, Greece

5.1   Byte-Sliced Crossbar Switches

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Byte-Sliced Crossbars: halfway between a crossbar and a fabric

Byte Slicing Concept: Control chip, Datapath chip

Version 2: single-chip control+datapath with Speed Expansion Option

Configuration with x4 speed expansion

References:

  • N. McKeown, M. Izzard, A. Mekkittikul, W. Ellersick, M. Horowitz: "Tiny Tera: a Packet Switch Core", IEEE Micro, Jan.-Feb. 1997, pp. 26-33.
  • F. Abel, C. Minkenberg, R. Luijten, M. Gusat, I. Iliadis: "A Four-Terabit Packet Switch Supporting Long Round-Trip Times", IEEE Micro Magazine, vol. 23, no. 1, Jan./Feb. 2003, pp. 10-24. An earlier version appeared as Research Report RZ 3430, IBM Zurich Research Lab, (# 93609) Jan. 2002, 10 pages; preprint available on-line through domino.watson.ibm.com/library

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