CS-534: Packet Switch Architecture
Spring 2003
Department of Computer Science
© copyright: University of Crete, Greece

Schedule of Lectures:

DESIRABLE SCHEDULE:                        ACTUAL SCHEDULE:

01a  Overview                              17/2: Overview
01b  Shared Links, Serial/Parallel, TDM    19/2: Links, Serial/Parallel
        Ex.1: Rate & throughput calc.           Ex.1: 19/2 --> 24/2

02a  Ckt.Sw., TSI, TDM Xbar Scheduling     24/2: TDM, Ckt.Sw., TSI
02b  Basic Concepts of Pck Switching #1    26/2: TDM Xbar Sched, TSSST
        Ex.2: TST ckt. switch scheduling        Ex.2: 24/2 --> 05/3

03a  Basic Concepts of Pck Switching #2    03/3: [instructor out-of-t.]
03b  Basic Concepts #3, Switch Gener.      05/3: Basic Concepts #1
        Ex.3: Int.bl., cut-thru, sw.gen.        Ex.3: 05/3 --> 12/3

04a  Ch.3: SRAM: On-chip, Off-chip         10/3: [Kathari Deutera]
04b  DRAM, Synchronizers, Elastic Buffers  12/3: Basic Concepts #2
                                           14/3: BC#3, on-chip SRAM
        Ex.4: RAM acc. rate, segment rate       Ex.4: 14/3 --> 24/3

05a  Circular buf. FIFO, multi-Queue #1    17/3: off-chip SRAM, DRAM#1
05b  Multi-Queue Data Structures #2        19/3: DRAM#2, elastic
        Ex.5: Linked List Multi-Q memories

06a  Multicast Queues & Data Structures    24/3: multi-Q data str.#1
06b  Ch.4: OutQ family, perf, block-xpoint 26/3: multiQ#2, mcast-Q.#1
        Ex.6: more lnk'd list multi-Q mem.

07a  ---  MIDTERM EXAM ---                 31/3: mcast#2, Q'Arch.#1
07b  wide/pipe.mem, inputQ/HOL bl., perf.  02/4: "epanalipsi"
        Ex.7: queueing arch. cost (SRAM's) 04/4: MIDTERM EXAM

08a  per-out. inQ (VOQ), Crossbar Sched.  07/4: wide, interleaved mem's
08b  speed-up, CIOQ, matching outQ        09/4: output queueing, inQ #1
        Ex.8: inQ sat.thrup., VOQ/xb sch.

09a  CICQ-buf.xbar/backpr., Qarch. cmp.   14/4: input queueing #2, VOQ
09b  Fabrics w. Int. Backpr., flow ctrl.  16/4: xbar sched, CIOQ-speedup
        Exercises 9: Flow control

10a  Flow Control, Multilane Backpressure 05/5: Byte-Slicing, Benes Intr
10b  Ch.5: Switching Fabric Topologies #1 07/5: Clos, Benes, inv.mux #1
        *** Paper Reading Assignments ***

11a  Fabrics #2, Bufferless/Buffered      12/5: inv.mux2, fatTr,buf'less
11b  Output Scheduling for QoS #1         14/5: bufferless fab, FC intro
        Ex.10: Switching fabric topologies

12a  Output Scheduling for QoS #2         19/5: Flow Control, Credits #1
12b  Other Adv. Topics, Overflow time.    21/5: Credits #2, per-flow #1
        Exercises 11: Scheduling

13a  Student Presentations #1             26/5: Sw.Fabr.w.Int.Backpres.
13b  Student Presentations #2             28/5 (3 hrs): Scheduling (ch7)


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© copyright University of Crete, Greece.
Last updated: 6 June 2003, by M. Katevenis.