CS-534: Packet Switch Architecture
Spring 2005		 Department of Computer Science
© copyright: University of Crete, Greece

2.2   Off-Chip Memory Technologies

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2.2.1   Synchronous RAM Chip Interfaces, DDR Timing

SRAM with address and data registers (pipelined, clocked, synchronous interface)

DDR (Double Data Rate) Timing

Source-Synchronous Data Clocking

2.2.2   Bus Turn-Around Overhead Minimization

Separate D(in) and Q(out) versus Shared DQ Data Bus

QDR (Quad Data Rate) SRAM

Reference: the "QDR Partnership" Web Site: http://www.qdrsram.com/.

Example QDR SRAM: Micron MT54V512H18

Micron Technology Inc.

Reference 1: Micron "MT54V 512H 18" 512 K x 18 bit (9 Mbit) QDR SRAM: PDF data sheet available on-line. For product availability information see the Component Selector Guide.

Reference 2 (Jan. 2002): Alpine Microsystems plans to introduce (Q1-Q2 of 2002) the "PacketRAM Family" of pipelined QDR SRAMS, offering 96 Gbps at 333 MHz, and higher speeds later on.

ZBT (Zero Bus Turn-around) Timing

Example DDR SRAM: Micron MT57V256H36

Micron Technology Inc.

Reference: Micron "MT57V 256H 36" 256 K x 36 bit (9 Mbit) DDR SRAM: PDF data sheet available on-line. For product availability information see the Component Selector Guide.

2.2.3   Dynamic RAM, Internal Bank Interleaving

DRAM Basics: Row Address, Column Address, Precharge

Example DDR SDRAM: Micron MT46V2H32

Single-Bank Read Access

Single-Bank Write Access

Multiple Accesses to Different Columns in the same Row of a Bank

Multi-Bank Operation: Memory Interleaving

Micron Technology Inc.

Reference: Micron "MT46V 2M 32" 2 M x 32 bit (64 Mbit) DDR SDRAM: PDF data sheet available on-line. For product availability information see the Component Selector Guide.

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Last updated: 17 Apr. 2005, by M. Katevenis.