1.2 Clock Domains and Elastic Buffers (U.Crete, CS-534)

CS-534: Packet Switch Architecture
Spring 2004

Department of Computer Science
© copyright: University of Crete, Greece

1.2 Clock Domains and Elastic Buffers

[Up - Table of Contents]
[Prev - 1.1 Rate and Throughput]

[1.3 Mux, Output Contention - Next]

1.2.0 Multiple Clock Domains: Metastability and Synchronization

The need for cross-clock-domain communication

Intf. slightly diff. ck frequ: slow-to-fast: insert idle symbols

Intf. slightly diff. ck frequ: fast-to-slow: remove idle symbols

Reference: W. Dally, J. Poulton: "Digital Systems Engineering", Cambridge University Press, 1998, ISBN 0-521-59292-5 (section 10.2: Synchronization Fundamentals).

1.2.1 Serial Signals across Clock Domains: Sampling Time

Was the signal sampled before or after its change?

1.2.2 Parallel Signals across Clock Domains: Elastic Buffers

Asynchronous sampling of multibit signals (almost impossible)

Elastic Buffer (2-asynchronous-port SRAM)

Reminder: Circular Array Implementation of FIFO Queue

One-Hot Pointer Encoding

Empty/Full FIFO Detection using One-Hot Pointer Encoding

Empty and Full flags: asynchronous to either clock

Synchronized Empty/Full Generation for High-Throughput Operation

Synchronized Empty/Full Generation: explanations

Reference: W. Dally, J. Poulton: "Digital Systems Engineering", Cambridge University Press, 1998, ISBN 0-521-59292-5 (section 10.3: Synchronizer Design, especially section 10.3.4.2).

[Up - Table of Contents]
[Prev - 1.1 Rate and Throughput]

[1.3 Mux, Output Contention - Next]

Up to the Home Page of CS-534