CS-425: Computer Systems Architecture
Department of Computer Science, University of Crete
AMD quad-core processor, courtesy of AMD Class meets Monday, Wednesday, 13.15–15.00 in room Rho Alpha 203 (Knossos campus). Friday classes will be held as needed at the same time in Rho Alpha 203, to make up in case of instructor's absence during regular class meeting times.

Midterm TBA

Home   Syllabus   Lectures   Assignments   Personnel 

Textbook and Reading Material
H&P: Computer Architecture, 4th Edition
Course textbook: Hennessy and Patterson, Computer Architecture, A Quantitative Approach, 4th Edition. Available in Greek (Tziolas publishers, translation by D. Pnevmatikatos, D. Serpanos and G. Stamoulis). ISBN 9789604180769.

Additional reading: Shen and Lipasti, Modern Processor Design, Fundamentals of Superscalar Processors, McGraw Hill, 2005, ISBN 0-07-059033-8.
Additional reading material will be posted as needed, during classes. Reading material includes Chapters from other textbooks (in English) and technical papers from conferences or journals covering the field of Computer Architecture.

Lectures

Class Topic Slides Reading list Assignments
24/9 Welcome and introduction Slides Chapter 1 (1.1-1.3) from course textbook
26/9 Metrics Slides Chapter 1 (1.4-1.12) from course textbook
1/10 Pipelining review Slides Appendix A (A.1.A.3) from course textbook
3/10 Dynamic scheduling with Scoreboard Slides Appendix A (A.7.A.8) from course textbook
10/10 Dynamic scheduling with Tomasulo Slides Chapter 2 (2.4,2.5) from course textbook Homework 1
12/10 Dynamic scheduling with Tomasulo Handouts from 10/10 Tomasulo's original paper
19/10 ILP and Static scheduling Slides Section 2.2, Appendix G(G.1-G.3) from course textbook
22/10 Branch prediction Slides Sections 2.3, 2.9 (pages 121-126), Appendix G(G.4) from course textbook. Alternative implementations of two-level adaptive branch predictors Homework 2
24/10 Precise Exceptions and Speculation Slides Section 2.6, Appendix A(A.4), Section 2.9 (pages 127-129) from course textbook
5/11 Programming Assignment 1 is ready! Programming Assignment 1
29/10 Multiple issue processors (statically and dynamically scheduled) Slides, handout 2up, handout 4up, updated on Oct. 31, 08:18Chapter 3, Section 3.6 from course textbook, Chapter 5, Section 5.1 from book “Modern Processor Design: Fundamentals of Superscalar Processors”, by Lipasti and Shen
31/10 SpeculationSlides, handout 2up, handout 4up, updated on Oct. 31, 08:19Chapter 3, Section 3.7 from course textbook, Chapter 5, Sections 5.2–5.3 from book “Modern Processor Design: Fundamentals of Superscalar Processors”, by Lipasti and Shen
4/11 Limits of ILPSlides, handout 2up, handout 4up, updated on Oct. 31, 19:44Chapter 3, Sections 3.8–3.10 from course textbook, Limits of Instruction-Level Parallelism, by David Wall, WRL Research Report 93/6Programming Assignment 1, updated Oct. 31 19:45
12/11 Software techniques for ILP: Static scheduling and VLIW Slides, handout 2up, handout 4up, updated on Nov. 4, 21:36Chapter 4, Sections 4.1–4.3 from course textbook
19/11 Software pipelining. Introduction to vector processorsSlides, handout 2up, handout 4up, updated on Nov. 23, 21:22 reading material from previous lecture, Appendix F from book Computer Architecture: A Quantitative Approach, Fourth Edition, by Hennessy and Patterson Homework 3
21/11 Cache memories: Design and performance analysisSlides, handout 2up, handout 4up, updated on November 28, 11:27 Chapter 5, Sections 5.1–5.3, from textbook Computer Architecture: A Quantitative Approach, Third Edition, by Hennessy and Patterson Homework 4
26/11 Cache design optimizationsSlides, handout 2up, handout 4up, updated on Nov. 25, 22:49 Chapter 5, Sections 5.4–5.7, from textbook Computer Architecture: A Quantitative Approach, Third Edition, by Hennessy and Patterson
28/11 Hardware prefetchingSlides, handout 2up, handout 4up, updated on Nov. 26, 15:11 Chapter 3, Section 3.1, from textbook Memory Systems: Cache, DRAM, Disk, by Jacob, Ng, and Wang
3/12 DRAM TechnologiesSlides, handout 2up, handout 4up, updated on Dec. 1, 12:00 Chapter 7, Sections 7.1–7.5, from textbook Memory Systems: Cache, DRAM, Disk, by Bruce Jacob, Spencer W. Ng, and David T. Wang
3/12 Multiprocessor ArchitecturesSlides, handout 2up, handout 4up, updated on Jan. 12 2011, 01:03 Chapter 6, Sections 6.1–6.2, from textbook Computer Architecture: A Quantitative Approach, Third Edition
3/12 Snooping Coherence ProtocolsSlides, handout 2up, handout 4up, updated on Jan. 12 2011, 01:04 Chapter 6, Section 6.3 from textbook Computer Architecture: A Quantitative Approach, Third Edition Programming Assignment 2

I. Mavroidis and C. P. Sotiriou - Last Modification - 10/12/2012.