4. Switch Queueing Architectures & Performance

Subsections in the current document:

• 4.1 Output Queueing Family
• 4.2 Shared Buffer Implementation: Wide Memory, Pipelined Memory
• 4.3 Input Queueing Family
• 4.4 Combinations and Variations
• 4.5 Queueing Architecture Summary and Comparisons
• 4.6 Input Queueing Throughput Analysis
• 4.7 Input Queueing Delay Analysis and Variants
• 4.8 Output Queueing Performance Analysis
• 4.9 Scheduling for Input Buffered Switches

Introduction

4.1 Output Queueing Family

4.2 Shared Buffer Implementation: Wide Memory, Pipelined Memory

See the paper: M. Katevenis, P. Vatsolaki, A. Efthymiou: Pipelined Memory Shared Buffer for VLSI Switches, Proceedings of the ACM SIGCOMM '95 Conference, Cambridge, MA USA, 30 August - 1 Sep. 1995, pp. 39-48; USA patent number 5,774,653.

4.3 Input Queueing Family

4.4 Combinations and Variations

4.5 Queueing Architecture Summary and Comparisons

4.6 Input Queueing Throughput Analysis

See the papers:

M. Karol, M. Hluchyj, S. Morgan: "Input versus Output Queueing on a Space-Division Packet Switch", IEEE Trans. on Communications, vol. 35, no. 12, Dec. 1987, pp. 1347-1356.

M. Hluchyj, M. Karol: "Queueing in High-Performance Packet Switching", IEEE Journal on Sel. Areas in Commun. (JSAC), vol. 6, no. 9, Dec. 1988, pp. 1587-1597.

4.7 Input Queueing Delay Analysis and Variants

See the paper: J. Hui, E. Arthurs: "A Broadband Packet Switch for Integrated Transport", IEEE Journal on Sel. Areas in Commun. (JSAC), vol. 5, no. 8, Oct. 1987, pp. 1264-1273.

4.8 Output Queueing Performance Analysis

4.9 Scheduling for Input Buffered Switches

See papers number 3 through 7 in the Reading List.